How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Part one of a five-part series, this article teaches a methodology to interpret statistics gathered during test runs and use those interpretations to improve parallel code.
Intel® Cilk™ Plus is an extension to the C and C++ languages to support data and task parallelism. It provides three new keywords to i
If printf or fprintf functions cause transaction aborts, use Intel® Processor Trace as a work-around.
Get an overview of parallelization using the Intel® MPI Library and links to additional documentation.
This article discussions parallelization and provides links that will help you understand your programming environment and evaluate the suitability of your app.
This article is part of the Intel® Modern Code Developer Community documentation which supports developers in leveraging application performance in code through a systematic step-by-step optimization framework methodology. This article addresses: Thread level parallelization.
Learn how to use Offload over Fabric software for a server migration path.
The Intel® Xeon Phi™ processor, code named Knights Landing, is part of the second generation of Intel Xeon Phi products. Knights Landing supports Intel® AVX-512 instructions, specifically AVX-512F (foundation), AVX-512CD (conflict detection), AVX-512ER (exponential and reciprocal) and AVX-512PF (prefetch).
Download this guide for developing multithreaded applications, which also includes general topics such as application threading and synchronization.