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Article

OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Автор: Последнее обновление: 31.07.2019 - 14:30
Article

Superscalar Programming 101 (Matrix Multiply) Part 1 of 5

Part one of a five-part series, this article teaches a methodology to interpret statistics gathered during test runs and use those interpretations to improve parallel code.
Автор: jimdempseyatthecove (Blackbelt) Последнее обновление: 04.07.2019 - 22:00
Article

Improving Averaging Filter Performance Using Intel® Cilk™ Plus

Intel® Cilk™ Plus is an extension to the C and C++ languages to support data and task parallelism.  It provides three new keywords to i

Автор: Anoop M. (Intel) Последнее обновление: 12.12.2018 - 18:00
Блоги

Debug Intel® Transactional Synchronization Extensions

If printf or fprintf functions cause transaction aborts, use Intel® Processor Trace as a work-around.
Автор: Roman Dementiev (Intel) Последнее обновление: 04.07.2019 - 17:00
Article

Parallelization Using Intel® MPI

Get an overview of parallelization using the Intel® MPI Library and links to additional documentation.
Автор: админ Последнее обновление: 30.09.2019 - 17:30
Article

Programming and Compiling for Intel® Many Integrated Core Architecture

This article discussions parallelization and provides links that will help you understand your programming environment and evaluate the suitability of your app.
Автор: AmandaS (Intel) Последнее обновление: 30.09.2019 - 17:28
Article

Efficient Parallelization

This article is part of the Intel® Modern Code Developer Community documentation which supports developers in leveraging application performance in code through a systematic step-by-step optimization framework methodology. This article addresses: Thread level parallelization.
Автор: Ronald W Green (Blackbelt) Последнее обновление: 30.09.2019 - 17:28
Article

Offload Computations from Servers with an Intel® Xeon Phi™ Processor

Learn how to use Offload over Fabric software for a server migration path.
Автор: Jan Z. (Intel) Последнее обновление: 15.10.2019 - 15:30
Article

How to detect Knights Landing AVX-512 support (Intel® Xeon Phi™ processor)

The Intel® Xeon Phi™ processor, code named Knights Landing, is part of the second generation of Intel Xeon Phi products. Knights Landing supports Intel® AVX-512 instructions, specifically AVX-512F (foundation), AVX-512CD (conflict detection), AVX-512ER (exponential and reciprocal) and AVX-512PF (prefetch).
Автор: James R. (Blackbelt) Последнее обновление: 15.10.2019 - 15:30
Article

Intel Guide for Developing Multithreaded Applications

Download this guide for developing multithreaded applications, which also includes general topics such as application threading and synchronization.
Автор: админ Последнее обновление: 15.10.2019 - 16:40