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Article

Intel® Xeon® Processor E7 v3 Product Family

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Блоги

Big Performance Gains for Big Data

Imagine two teams of data analysts working on the same goal: to extract usable business intelligence (BI) from massive, growing data sets.

Автор: Последнее обновление: 28.01.2019 - 15:20
Блоги

Digital Transformation is in Your Future

Автор: Последнее обновление: 13.07.2018 - 14:32
Article

Palestra: Como otimizar seu código sem ser um "ninja" em Computação Paralela

Não perca a palestra "Como otimizar seu código sem ser um "ninja" em Computação Paralela" da Intel que será ministrada durante a Semana sobre Programação Massivamente Paralela em Petrópolis, RJ, no Laboratório Nacional de Computação Científica. Data: 02/02/2016 - 11h30 Local: LNCC - Av. Getúlio Vargas, 333 - Quitandinha - Petrópolis/RJ
Автор: Igor F. (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Proof Points for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

Cache Allocation Technology (CAT) provides benefits across a number of usages, as described in the previous article in this series. This article briefly describes one proof point from the data center (prioritizing a web server to improve its performance) and one from communications (protecting a key communications infrastructure virtual machine (VM)).
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

This article provides a snapshot of some of the software-enabling collateral available for the Cache Allocation Technology (CAT) feature.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Introduction to Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family

Introduction

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Usage Models for Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family

Introduction

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Proof Points: Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family

This article provides a number of Memory Bandwidth Monitoring (MBM) example proof points and discussion fitting with the usage models described in previous articles.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40