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Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions

Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.

Автор: gaston-hillar (Blackbelt) Последнее обновление: 06.07.2019 - 17:00
Блоги

The JITter Conundrum - Just in Time for Your Traffic Jam

In interpreted languages, it just takes longer to get stuff done - I earlier gave the example where the Python source code a = b + c would result in a BINARY_ADD byte code which takes 78 machine instructions to do the add, but it's a single native ADD instruction if run in compiled language like C or C++. How can we speed this up? Or as the performance expert would say, how do I decrease...
Автор: David S. (Blackbelt) Последнее обновление: 04.07.2019 - 20:00
Article

Palestra: Como otimizar seu código sem ser um "ninja" em Computação Paralela

Não perca a palestra "Como otimizar seu código sem ser um "ninja" em Computação Paralela" da Intel que será ministrada durante a Semana sobre Programação Massivamente Paralela em Petrópolis, RJ, no Laboratório Nacional de Computação Científica. Data: 02/02/2016 - 11h30 Local: LNCC - Av. Getúlio Vargas, 333 - Quitandinha - Petrópolis/RJ
Автор: Igor F. (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Live Webinar: Boost Python* Performance with Intel® Math Kernel Library

Python* is a popular open-source scripting language known for its easy-to-learn syntax and active developer community.
Автор: Mike P. (Intel) Последнее обновление: 07.06.2017 - 10:28
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Автор: David Mulnix (Intel) Последнее обновление: 06.07.2019 - 16:40
Блоги

Doubling the Performance of OpenStack Swift with No Code Changes

My current gig is mostly about performance. I manage a group of software engineers dedicated to the languages becoming really important to the cloud and the datacenter.

Автор: David S. (Blackbelt) Последнее обновление: 06.07.2019 - 17:10
Article

Free access to Intel® Compilers, Performance libraries, Analysis tools and more...

Intel® Parallel Studio XE is a very popular product from Intel that includes the Intel® Compilers, Intel® Performance Libraries, tools for analysis, debugging and tuning, tools for MPI and the Intel® MPI Library. Did you know that some of these are available for free? Here is a guide to “what is available free” from the Intel Parallel Studio XE suites.
Автор: админ Последнее обновление: 21.03.2019 - 12:00
Article

Manage Deep Learning Networks with Caffe* Optimized for Intel® Architecture

How to optimize Caffe* for Intel® Architecture, train deep network models, and deploy networks.
Автор: Andres Rodriguez (Intel) Последнее обновление: 11.03.2019 - 13:17
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Автор: Последнее обновление: 06.07.2019 - 16:40
Article

Introducing DNN primitives in Intel® Math Kernel Library

Please notes: Deep Neural Network(DNN) component in MKL is deprecated since intel® MKL ​2019 and will be removed in the next intel® MKL Release.

Автор: Vadim Pirogov (Intel) Последнее обновление: 21.03.2019 - 12:00