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Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions

Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.

Автор: gaston-hillar (Blackbelt) Последнее обновление: 06.07.2019 - 17:00
Article

Intel® Xeon® Processor E7 v3 Product Family

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Intel® Parallel Computing Center at Georgia Institute of Technology

The Intel® Parallel Computing Center (Intel® PCC) on Big Data in Biosciences and Public Health is focused on developing and optimizing parallel algorithms and software on Intel® Xeon® Processor and Intel® Xeon Phi™ Coprocessor systems for handling high-throughput DNA sequencing data and gene expression data.
Автор: админ Последнее обновление: 14.11.2017 - 08:27
Article

Caffe* Training on Multi-node Distributed-memory Systems Based on Intel® Xeon® Processor E5 Family

Caffe is a deep learning framework developed by the Berkeley Vision and Learning Center (BVLC) and one of the most popular community frameworks for image recognition. Caffe is often used as a benchmark together with AlexNet*, a neural network topology for image recognition, and ImageNet*, a database of labeled images.
Автор: Gennady F. (Blackbelt) Последнее обновление: 05.07.2019 - 14:54
Article

Palestra: Como otimizar seu código sem ser um "ninja" em Computação Paralela

Não perca a palestra "Como otimizar seu código sem ser um "ninja" em Computação Paralela" da Intel que será ministrada durante a Semana sobre Programação Massivamente Paralela em Petrópolis, RJ, no Laboratório Nacional de Computação Científica. Data: 02/02/2016 - 11h30 Local: LNCC - Av. Getúlio Vargas, 333 - Quitandinha - Petrópolis/RJ
Автор: Igor F. (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

This article provides a snapshot of some of the software-enabling collateral available for the Cache Allocation Technology (CAT) feature.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Live Webinar: Boost Python* Performance with Intel® Math Kernel Library

Python* is a popular open-source scripting language known for its easy-to-learn syntax and active developer community.
Автор: Mike P. (Intel) Последнее обновление: 07.06.2017 - 10:28
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Автор: David Mulnix (Intel) Последнее обновление: 06.07.2019 - 16:40
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One Hero’s Modern Code is Changing the World!

The Intel® Modern Code Developer Program has the tools, knowledge and expertise to power your breakthrough Innovations.

Автор: админ Последнее обновление: 12.12.2018 - 18:00