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Terasic DE 10-Nano Development Board User Manual

DE 10-Nano User Manual.
Автор: админ Последнее обновление: 10.07.2018 - 08:00
Article

Exploring the HPS and FPGA onboard the Terasic DE10-Nano

Terasic DE10-Nano is a development kit that contains an Intel® Cyclone® device. The Intel® Cyclone® V device contains a Hard Processor System (HPS) and field-programmable gate array (FPGA) with a wealth of peripherals onboard for creating some interesting applications. One of the most basic things to accomplish with this system is to control the LEDs that are physically connected to the FPGA....
Автор: Rylee, Michael J (Intel) Последнее обновление: 10.07.2018 - 08:00
Article

A Scalable Path to Commercial IoT Solutions

Get to your development goal with hardware, software, plus data solutions that work together seamlessly, at scale and securely. From the cloud right out to the edge, Intel® IoT Technology offers a complete ecosystem for the connected future. A Smarter World—for Every Enterprise Moving forward is easier when you don’t have to innovate from scratch. Our complete dev kits, comprehensive code...
Автор: админ Последнее обновление: 10.07.2018 - 08:00
Article

Explore the GPIO Example Application

In this example application, you'll learn how to interact with the Terasic* DE10-Nano board's digital I/O.
Автор: админ Последнее обновление: 10.07.2018 - 08:00
Article

Adapting to Security Threats with FPGAs

Intel® Cyclone® V SoC FPGA devices are ideally suited for use in base stations and IoT gateways that must interact with a large network of sensors and actuators in a secure way. Interacting in a secure way means that the two communicating devices trust each other and that commands, messages, and other data passed between the two has not been modified or revealed to an unauthorized party...
Автор: админ Последнее обновление: 10.07.2018 - 08:00
Article

Build a Custom Hardware System

This tutorial shows you how to use the Qsys* system integration tool to create a custom Field Programmable Gate Array (FPGA) hardware design using IP available in the Intel® FPGA IP library. Qsys speeds embedded system design by creating a configurable interconnect between IP blocks. Developers who create their own IP blocks can publish them to the Qsys IP library for reuse in their systems
Автор: админ Последнее обновление: 10.07.2018 - 08:00
Article

OpenVINO™ 工具套件版本说明

OpenVINO™ 2018 R3 Release - Gold release of the Intel® FPGA Deep Learning Acceleration Suite accelerates AI inferencing workloads using Intel® FPGAs that are optimized for performance, power, and cost, Windows* support for the Intel® Movidius™ Neural Compute Stick, Python* API preview that supports the inference engine, Open Neural Network Exchange (ONNX) Model Zoo provides initial support for...
Автор: Deanne Deuermeyer (Intel) Последнее обновление: 22.10.2018 - 23:52
Article

Release Notes for Intel® Distribution of OpenVINO™ toolkit 2018

Introduction

NOTE: The Intel® Distribution of OpenVINO™ toolkit was formerly known as the Intel® Computer Vision SDK

Автор: Andrey Z. (Intel) Последнее обновление: 02.04.2019 - 11:45
Article

Release Notes for Intel® Distribution of OpenVINO™ toolkit 2019

OpenVINO™ 2019 R2.01 Release
Автор: Deanne Deuermeyer (Intel) Последнее обновление: 21.08.2019 - 08:54