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Article

Intel® Xeon® Processor E7 v3 Product Family

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
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Academics Make Games Better - Foundations of Digital Games 2015

Foundations of Digital Games is a summit of innovators and influencers in gaming-related academia as well as the games industry itself. In what was originally “the premier educational conference for faculty who use game development to teach computer science concepts and principles”, it began in 2006 as Microsoft Academic Days on Game Development in Computer Science Education (GDCSE) and was...
Автор: Последнее обновление: 24.01.2018 - 12:12
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The JITter Conundrum - Just in Time for Your Traffic Jam

In interpreted languages, it just takes longer to get stuff done - I earlier gave the example where the Python source code a = b + c would result in a BINARY_ADD byte code which takes 78 machine instructions to do the add, but it's a single native ADD instruction if run in compiled language like C or C++. How can we speed this up? Or as the performance expert would say, how do I decrease...
Автор: David S. (Blackbelt) Последнее обновление: 04.07.2019 - 20:00
Article

Caffe* Training on Multi-node Distributed-memory Systems Based on Intel® Xeon® Processor E5 Family

Caffe is a deep learning framework developed by the Berkeley Vision and Learning Center (BVLC) and one of the most popular community frameworks for image recognition. Caffe is often used as a benchmark together with AlexNet*, a neural network topology for image recognition, and ImageNet*, a database of labeled images.
Автор: Gennady F. (Blackbelt) Последнее обновление: 05.07.2019 - 14:54
Article

基于英特尔® 至强™ 处理器 E5 产品家族的多节点分布式内存系统上的 Caffe* 培训

Caffe is a deep learning framework developed by the Berkeley Vision and Learning Center (BVLC) and one of the most popular community frameworks for image recognition. Caffe is often used as a benchmark together with AlexNet*, a neural network topology for image recognition, and ImageNet*, a database of labeled images.
Автор: Gennady F. (Blackbelt) Последнее обновление: 05.07.2019 - 14:55
Article

Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Proof Points for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

Cache Allocation Technology (CAT) provides benefits across a number of usages, as described in the previous article in this series. This article briefly describes one proof point from the data center (prioritizing a web server to improve its performance) and one from communications (protecting a key communications infrastructure virtual machine (VM)).
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

This article provides a snapshot of some of the software-enabling collateral available for the Cache Allocation Technology (CAT) feature.
Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Introduction to Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family

Introduction

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40
Article

Usage Models for Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family

Introduction

Автор: Nguyen, Khang T (Intel) Последнее обновление: 06.07.2019 - 16:40