Intel® Developer Zone:
Защита и шифрование

Новые команды AES

  • Новые инструкции Intel® AES (Intel® AES-NI)
    Обзор новых инструкций шифрования Intel® AES-NI, улучшающих алгоритм шифрования AES и ускоряющих шифрование данных.
  • Защита предприятия с помощью Intel® AES-NI
    Узнайте, почему криптография так популярна на современном рынке, особенно на рынке решений для предприятий.
  • Команды Intel® AES-NI
    Описание шести новых команд, составляющих набор команд AES-NI. Эти команды отвечают за ряд высокопроизводительных компонентов алгоритма AES.

Цифровой генератор случайных чисел

Расширения набора команд для архитектуры Intel

  • Intel® Memory Protection Extensions (Intel® MPX) — это название расширений для архитектуры Intel, созданных для повышения надежности программного обеспечения.
  • Intel® Software Guard Extensions (Intel® SGX) — это название расширений архитектуры Intel, созданных для повышения безопасности программного обеспечения с помощью механизма инверсионной изоляции (inverse sandbox).
  • Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) — это семейство из семи инструкций, основанных на расширениях Intel® Streaming SIMD Extensions (Intel® SSE), которые используются совместно для повышения производительности механизмов SHA-1 и SHA-256, работающих на базе архитектуры процессоров Intel.
The Intel® Core™ M Processor
- Colleen Culbertson (Intel)Опубликовано: 09/29/20140
This article, aimed at developers, will provide a glimpse into this 64-bit, multi-core SOC processor, with an overview of the available Intel technologies, including Intel® HD Graphics 5300.
Intel® Device Protection Technology and McAfee Mobile Security for Android*
- EGOR F. (Intel)Опубликовано: 09/11/20140
Intel® Device Protection Technology Recent industry reports indicate Android* is the OS in more than 59 percent of laptops, tablets and smartphones worldwide. While its growth has been explosive and continues, vulnerabilities exist because Android is an open platform. Additionally, corporate IT ...
Intel® Xeon™ E5-2600 v3 Product Family
- BELINDA L. (Intel)Опубликовано: 09/08/20140
Based on Intel® Core™ microarchitecture (formerly codenamed Haswell) and manufactured on 22-nanometer process technology, these processors provide significant performance over the previous-generation Intel® Xeon™ processor E5-2600 v2 product family. This is the first Intel® Xeon® processor fami...
How to use the rdrand engine in OpenSSL for random number generation
- John Mechalas (Intel)Опубликовано: 07/30/20140
The OpenSSL* ENGINE API includes an engine specifically for Intel® Data Protection Technology with Secure Key. When this engine is enabled, the RAND_bytes() function will exclusively use the RDRAND instruction for generating random numbers and will not need to rely on the OS's entropy pool for re...
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Технология Intel® Virtualization (Intel® VT)

IDF'14 Software Networking Webinars
- Mike Pearce (Intel)Опубликовано: 01/19/20150
DATS002 - Virtualizing the Network to Enable a Software Defined Infrastructure Intel is heavily investing in products and technologies for network overlays, network function virtualization (NFV) and software defined networking (SDN) to help drive the network hardware architectural transformatio...
Intel® Hardware Accelerated Execution Manager
- adminОпубликовано: 10/24/201424
The Intel Hardware Accelerated Execution Manager (Intel® HAXM) is a hardware-assisted virtualization engine (hypervisor) that uses Intel Virtualization Technology (Intel® VT) to speed up Android app emulation on a host machine. In combination with Android x86 emulator images provided by Intel and...
Intel® Xeon® Processor E5-2600 V3 Product Family Technical Overview
- Sreelekshmy Syamalakumari (Intel)Опубликовано: 09/12/20140
Contents 1. Executive Summary2. Introduction3. Intel Xeon processor E5-2600 V3 product family enhancements.   3.1 Intel® Advanced Vector Extensions 2 (Intel® AVX2) Instructions   3.2 Haswell New Instructions (HNI)   3.3 Support for DDR4 memory   3.4 Power Improvements4. Grantley platform im...
Getting Kernel-Based Virtual Machine (KVM) to Work with Intel® Xeon Phi™ Coprocessors
- loc-nguyen (Intel)Опубликовано: 05/29/20140
The current Kernel-based Virtual Machine (KVM) software does not recognize the existence of Intel® Xeon Phi™ coprocessors. In order to make the KVM recognize the coprocessors, we provide patches under the GPL license, to rebuild the kernel and qemu-kvm packages. The patches provided here are used...
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Intel VT-D and Intel X99 motherboards
- Ward H.0
Hi, I am thinking of buying a X99 motherboard that I can use for Vmware Workstation. The two brands that I am thinking of are ASUS and GigaByte. I have been looking into the Virtualization and plan on running VMWare Workstation 11.  So virtualize windows Server 2012, Windows 8.1 etc. Plus VMWare ESXi. So I think for the last one I need Vt-d. Now I have notice the the ASUS MB's have a few more options for VTD like: Vtd Azalea VCp optimizations. Interrupt Remapping Coherency Support (Non-ISoch) Coherency Support (ISoch) However the GigaByte board only allows me to turn VT-d on and off. So since I can't control these options would they be on by default on the GigaByte, is there anything 'Disadvantage' I have not being able to control them? (Or is all this a bit of a non-issue ?) BTW - I can understand people here might not know specifically about VMWare or the motherboards in question. For example I am wondering if say a board supports VT-d means that these options are inclu...
RSM and multiple cores
- MP1
Hi all, I am trying to understand a technology that makes use of SMM in relation to hypervisors (hypercheck), and I have a number of questions about SMM in general - I hope I am posting in the right forum. I'd be interested to understand the following: 1) I know that on SMI asserting, all cores (at different interruptible boundaries) will enter SMM: are there spurious cases where SMM is triggered on only less cores? 2) The RSM instruction is said to return the processor to the not-SMM state. Does it need to be executed on every processor in SMM mode? 3) If I am in SMM mode with all my cores (i.e. I wait until them all are in SMM with a mutex), if I execute RSM from one core, does it resume normal operations (i.e. the kernel code it was executing) while the others are left in SMM mode? I am asking because the Default Treatment of RSM (33.14.2) is not exactly clear to me in Intel's doc.   Thanks in advance.    
DCBX on XL710
- Chakravarthy N.1
Hi, I am trying to configure DCBX & ETS on Intel XL710 in Linux. Is it currently supported? dcbtool reports DCBX is not enabled and I could not find other any linux utility to configure ETS. Please let me know , if there is any config guide I can refer to to get it working. Thanks ~Chakri
Assign pages to VT-D devices
- steven7653
Need some help understanding the theory of operation for implementing Vt-D.  I've been through the manual a couple of times.  The part I'm having trouble understanding is when we assign the page tables to the root complex structures.  How does the guest know which frames it's allowed to assign for DMA use?  The only work around I could think of is to either A do a VMCALL and ask, or B mirror the entire range the guest is allowed to access vie EPT and assign that to the root complex structure as well.     
How to Teach my processor to support hardware virtualization?
- Aleksey C.2
  My processor (Intel Pentium dual-core T4200) does not support hardware virtualization. Can I solve the problem by any software? Thanks a lot for your advice.
How to handle GUID_ZPixelFormats in graphics card driver with Direct3D DirectDraw and DXVA under XDDM
- Letian Yi2
Hi all: I'm developing a virtual graphics card driver under XDDM. I have finished the DirectDraw part of the driver, and i can see the DirectDraw is enabled in dxdiag. Now i'm developing the D3D part, but when i handle GUID_ZPixelFormats in DdGetDriverInfo,  DirectDraw is disabled ! Does anyone know how to handle GUID_ZPixelFormats in DdGetDriverInfo ? My code: void DdInitZPixelFormats(PDD_GETDRIVERINFODATA lpGetDriverInfo) {     static const DDPIXELFORMAT g_zfmts[] =     {         {             sizeof(DDPIXELFORMAT), DDPF_ZBUFFER, 0,             { 16 }, { 0 }, { 0x0000ffff }, { 0x00000000 }, { 0x00000000 }         },         {             sizeof(DDPIXELFORMAT), DDPF_ZBUFFER, 0,             { 32 }, { 0 }, { 0x00ffffff }, { 0x00000000 }, { 0x00000000 }         },     };     DWORD num = sizeof(g_zfmts) / sizeof(DDPIXELFORMAT);     DWORD size = sizeof(g_zfmts);     UINT8 *buf = (UINT8 *)lpGetDriverInfo->lpvData;     memcpy(buf, g_zfmts, min(lpGetDriverInfo->dwExpe...
libiomp5md.dll missing
- Bob H.1
Is there a way for me to compile a fortran executable that I will not get this error when I try to run it on other computers? Bob
Extremely slow guest/host after VMLaunch
- roee l.4
Hey, I've been trying to run hypervisor on OSX 10.9 for a while and finally managed to set it up. Problem is that the CPU/CPUS I run the hypervisor on become extremely slow after VMLaunch. Everything seem right, I tested it using a simple user mode application which calls CPUID and the VM Exit handler I wrote successfully handles that. But the overall computer performance decreases significantly. The more cores I run VMLaunch on ,the slower it becomes. When run on all 4 cores I can't even move my mouse. What could it be?  The only VMExits I get are 'CPUID's which are probably done by the OS or some programs I use, but nothing else.  I hope that maybe one of you has experimented with it.   thanks!
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