Intel Transactional Synchronization Extensions (Intel TSX)

Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

In a previous post I discussed the Intel® Transactional Synchronization Extensions (Intel® TSX) technology released in the new generation of processors.  I described the Intel® Threading Building Blocks (Intel® TBB) implementation of the HLE interface (speculative_spin_mutex).  Now we can talk about the implementation of speculative_spin_rtw_mutex, a Preview Feature of TBB 4.2 Update 2.

Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transactional Synchronization Extensions (Intel® TSX) enabled.  Intel TSX can improve the performance of applications that use lock-based synchronization to protect data structure updates.  This feature allows multiple non-conflicting lock-protected changes to data to occur in parallel.

Fun with Intel® Transactional Synchronization Extensions

By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX). If you have not, I encourage you to check out this page (http://www.intel.com/software/tsx) before you read further. In a nutshell, Intel TSX provides transactional memory support in hardware, making the lives of developers who need to write synchronization codes for concurrent and parallel applications easier.

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Core™ microarchitecture code name Haswell. Intel® TSX implements hardware support for a best-effort “transactional memory”, which is a simpler mechanism for scalable thread synchronization as opposed to inherently complex fine-grained locking or lock-free algorithms. The extensions have two interfaces: Hardware Lock Elision (HLE) and Restricted Transactional Memory (RTM). 

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