Precise events are events for which the exact instruction addresses that caused the event are available.

You can configure these events to collect extended information, the values of all the registers evaluated at the IP of the interrupt, on IA-32 and Intel® 64 architecture systems. For example, on Intel Core™ 2 processor family, an L2 load miss that retrieves a cacheline can be identified with the MEM_LOAD_RETIRED.L2_LINE_MISS event. The register values and the disassembly allows the reconstruction of the linear address of the memory operation that caused the event.

Check the HOW configuration pane in the Configure Analysis window to make sure the events you use are precise. Usually precise events have a _PS postfix (for example, MEM_LOAD_RETIRED.FB_HIT_PS) in the Description column as follows:

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