I've learned the following formula to calculate the L1,L2,L3 Miss rate from another post which is given by @Kirill Rogozhin (Intel):
L3 cache miss
(180 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS) / CPU_CLK_UNHALTED.THREAD
L2 cache miss
((26 * MEM_LOAD_UPOS_RETIRED.LLC_HIT_PS) + (43 * MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS) + (60 * MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS)) / CPU_CLK_UNHALTED.THREAD
L1 cache miss
((12 * MEM_LOAD_UOPS_RETIRED.L2_HIT) + (26 * MEM_LOAD_RETIRED.LLC_HIT_PS) + (43 * MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS) + (60 * MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS) + (180 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS)) / CPU_CLK_UNHALTED.THREAD
However, there are 2 problems are encoutered during the process.
1.When I calculate the L3 miss rate, I get 90%. But my test application code is very simple. Therefore , the miss rate can't be that
big. And when I calculate the L2 miss rate, the result is bigger than 1 which is obvious not correct.
2.When I use hardware event :MEM_LOAD_RETIRED.LLC_HIT_PS , it shows that it's a invalid event. But on the platform of Sandybridge,
this event should be valid. So, I've no idea what's happening.
Any help would be appreciated.