Disabling cache coherancy

Disabling cache coherancy

Is there a way to disable cache coherency in intel sandybridge?

3 帖子 / 0 全新
最新文章
如需更全面地了解编译器优化,请参阅优化注意事项

Hello balu,
You can define a memory region as not cacheable.
Then reads from and writes to that region of memory are not checked for coherency.
Is this what you are looking for?
Pat

Hello Pat,

I was thinking if there is a way to disable MESI protocol (but still take advantage of the cache beingavailable) that is typically used to address "false sharing". Assuming that i guarantee there will be no "false sharing", can i disable the protocol effects (overheads) induced by MESI.

- Balu

发表评论

登录添加评论。还不是成员?立即加入