Front End Bound Due To Latency Caused By Switches From The DSB To The MITE

Front End Bound Due To Latency Caused By Switches From The DSB To The MITE

TITLE: Front End Bound Due To Latency Caused By Switches From The DSB To The MITE

ISSUE_NAME: Frontend^FE_latency^DSBtoMITE

DESCRIPTION:

Cycles the front end was bound due to the latency of switches from the DSB to the MITE

RELEVANCE:

When the front end cannot deliver uops when the back end is requesting uops, this can potentially indicate a front end limitation which is affecting performance.  With this metric, this latency is due to switches between the DSB (Decoded ICache) and the MITE (legacy decode pipeline).  A switch to the legacy decode pipeline from the Decoded ICache only occurs when a lookup in the Decoded ICache fails and usually costs anywhere from zero to three cycles in the front end of the pipeline.  Ideally the code should be laid out such that the uops come from the DSB instead of the MITE and avoid these switches.

EXAMPLE:

SOLUTION:

RELATED_SOURCES:

NOTES:

EQUATION:  DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD

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