Intel Intrinsic support for Atom Cloverview

Intel Intrinsic support for Atom Cloverview

Hi Everyone,

I have an application which was designed for inteli 7 using SSE to AVX, now I want the same application to run on Atom Processors.

I was recently browsing net for intrinsic support for Atom cloverview processors. Every where it mentions it support upto SSE3.

But that means it support just upto SSE3 or Supplemantry SSE3 is included in SSE3.

In Intel Atom architecture manual it says that all Atom processors Support Single-instruction multiple-data extensions up to SSE3 and SSSE3. 

Can somebody give me some clarity on the above, as I developing an application and I am not surte weather to include SSSE3 in my application.

If Intel Atom support SSSE3, that ease a lot of my pain

 

Thanks

11 帖子 / 0 全新
最新文章
如需更全面地了解编译器优化,请参阅优化注意事项

Hi Harrison-

I assume you're asking about "Clovertrail+" Atom processors, like the ones used in Android tablets like the Dell Venue 7. Is there a specific device you're targeting or testing on? 

I'm not 100% sure about Supplemental SSE3 support on that model, but I'm asking around to see if I can find an definitive answer for you. I'll post a reply here when I hear something. 

Thanks!

According to this article on optimizing media codecs for Atom processors:

“Intel Atom processor-based platforms support Intel SSE instruction codes, which includes MMX, MMXEXT, Intel SSE, SSE2, SSE3, SSSE3 and SSE4."

So it sounds like SSSE3 should be supported. Let me know if you run into any problems, or have any more questions. 

Hi Josh,

Thanks for the reply.

I am looking forward to develop an application which can run on all existing Atom prpcessors.

I have some clarity on other processors,but I am struck with clovertrail+ models z2560, z2580,z2520.

Wikipedia says that they supports upto SSSE3, but in intel official site it says it supports upto SSE3. Here is the link to intel official page

http://ark.intel.com/products/70100/intel-atom-processor-z2580-1mb-cache...

http://ark.intel.com/products/75203/Intel-Atom-Processor-Z2520-1MB-Cache...

Since this is the official intel blog,what ever it says will be followed for my development on Intel Atom. Can you please let me know whether I can support SSSE3 for the Clovertrail+ processors.

Can I use Bit manipulation instruction such as CMOV, LZCNT, FXSR to support my Clovertrail+ processors.

Is there any intel Intrinsic guide for Intel Atom, which mentions all instructions. Any help with links of study material with respect to Intel Atom intrinsic and assembly will be greatly appreciated.

NOTE: Presently I dont have specific hardware for Intel clovertrail+ processors. So I cant test its intrinsic support.

I am on serious deadline and any information regarding the above, will be great help to me.

 

Thanks in Advance

Harrison-

Let me check with the author of that article, who knows the specifics of SSSE3 support on these processors better than I do. I'll hopefully have an answer for you soon.

Hi,  I think those Intel Atom specsheets may be wrong, but I am double-checking.  Clovertrail+ supports instructions up to Supplemental SSE3 (i.e. SSSE3). 

Here is a link to an intrinsics guide:  http://software.intel.com/sites/landingpage/IntrinsicsGuide/

To see what is available on CLT+, click the boxes for MMX, SSE, SSE2, SSE3, and SSSE3.

Of the other 3 instructions you asked about, CMOV and FXSR are supported on CLT+.  However, CMOV is typically compiler-generated and there is no intrinsic to specifically target that instruction.  Typically a good compiler (like the Intel C/C++ compiler) will make proper usage of it.  I think FXSR refers to instructions which save and restore the Floating Point register state.  You probably don't need to use these unless you are writing an Operating System.  The LZCNT is not supported on CLT+.

You might also want to check out an article I wrote a few months about writing good SSE intrinsics code for Atom:

http://software.intel.com/node/473987

Thanks, and let us know if you have more questions.

-Mike

@Josh Thanks for the help. 

I am really disappointed from your response. As per my previous comments, I am positive that you understand my needs and yet my query is unresolved. I was expecting clear response from Intel after 6 days of the thread. 

I hope you are able to clear my doubts in your next response.

Thanks

H

@Micheal, Thanks for your reply. I found your article very helpful for my development.

Regarding the intrinsics guide, I have some doubt. I found CLT+ is based on Saltwell architecture, but I was no where able to locate saltwell in the guide. Did I miss any thing ? or it is again related to some misses in this very important document. 

I have attched the screenshot where i was able to see Ivy Bridge/ Haswell/ Nehalem etc but not Saltwell

I am on serious deadline and I will be very thankful to you if I can get a complete solid confirmation from Intel.

Because of this ambiguity in documents I don't want any red mark on my professional carrier. Please send me some links relating to support for SSS3 at the earliest. This thread was started on 22 Feb and I have already wasted a week with this confusion. 

I know Atom is relatively a new processor to Smartphones, but I request Intel to kindly maintain proper documentation so that people who are developing applications for Atom architecture are not discouraged.

Hope you understand my situation.

附件: 

附件尺寸
下载 Atom_Screenshot.docx180.37 KB

Hi,

Sorry for the confusion about CPU naming conventions.  Saltwell is the CPU which is included with the Clovertrail+ SOC platform (system-on-a-chip).  You can find instruction throughput and latency info in Chapter 14 of the optimization manual:

https://www-ssl.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html

Chapter 14 covers guidelines for Saltwell and all other Atom CPU's prior to "Silvermont".  Silvermont is covered in chapter 15.

I am certain that Saltwell supports instructions up to SSSE3.  Silvermont includes SSE4.1 instructions as well.  The instrinsics guide appears to only list the Intel(r) Core(tm) architecture CPU's, not the Atom CPU's.  In the future you can refer to the Optimization manual as I know that it gets updated and reviewed on a regular basis.  The intrinsics guide may be more informally handled.

Also, sorry for the delay in our response.  Unfortunately the forum didn't notify me when you posted, but feel free to email me at 'michael.stoner@intel.com'.  I'm curious to know the nature of your project and what you need help with specifically?

jumping on a slightly dated thread:

 

引文:

Harrisson M. 写道:

 

Wikipedia says that they supports upto SSSE3, but in intel official site it says it supports upto SSE3. Here is the link to intel official page

http://ark.intel.com/products/70100/intel-atom-processor-z2580-1mb-cache...

http://ark.intel.com/products/75203/Intel-Atom-Processor-Z2520-1MB-Cache...

The links you refer to both state that those formerly codenamed Cloverview SoCs support SSSE3, SSE3, and SSE2.

Hope that answers your question

(btw: Clover Trail / Clover Trail+ were the codenames for the platform)

@matthias, Thanks for the reply. I think you have really jumped onto outdated post.

I request you to kindly check the reply of Michael(Intel) " I think those Intel Atom specsheets may be wrong, but I am double-checking.  Clovertrail+ supports instructions up to Supplemental SSE3 (i.e. SSSE3)."

This issue was brought up by me on Sat, 02/22/2014 - 00:01 and has been very recently corrected. Please check the entire thread before coming to a wrong conclusion.

Only when the issue was raised the Intel Ark website was changed after a few months.

I am glad that necessary changes have been made, but in future I would request Intel to keep the websites updated otherwise anyone building the architecture on Intel Atom processors will face many challenges.

Hope that resolves your issue, Matthias.

Cheers for Michael Stoner(Intel) for being the most useful person to this thread and helping in resolving the issue. 

发表评论

登录添加评论。还不是成员?立即加入