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新鲜出炉!Intel® Xeon Phi™ Coprocessor High Performance Programming 
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Structured Parallel Programming
作者 Michael McCool、Arch D. Robison 和 James Reinders 采用一种基于结构性形式的途径,从而使该课题能为每一位软件开发人员所接受。

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Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness
作者:Indraneil Gokhale (Intel)张贴日期:09/15/20140
As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspects of their workloads: Vectorization/code generation Thread parallelism This article mainly talks a...
GROMACS recipe for symmetric Intel® MPI using PME workloads
作者:Heinrich Bockhorst (Intel)张贴日期:05/27/20150
Objectives This package (scripts with instructions) delivers a build and run environment for symmetric MPI runs. This file is actually the README of the package. Symmetric stands for employing a Xeon® executable and a Xeon Phi™ executable both running together exchanging MPI messages and collect...
Building and Running 3D-FFT Code that Leverages MPI-3 Non-Blocking Collectives with the Intel® Parallel Studio XE Cluster Edition
作者:Mark Lubin (Intel)张贴日期:05/26/20150
Purpose This application note assists developers with using Intel® Software Development Tools with the 3D-FFT MPI-3 based code sample from the Scalable Parallel Computing Lab (SPCL), ETH Zurich. Introduction The original 3D-FFT code based on the prototype library libNBC was developed to help i...
Intel® Xeon® Processor D Product Family Technical Overview
作者:David Mulnix (Intel)张贴日期:05/22/20150
Contents 1. Form Factor Overview2. Intel® Xeon® Processor D Product Family Overview3. Intel® Xeon® Processor D Product Family Feature Overview4. Intel® Xeon® processor D Product Family introduces new instructions as well as enhancements of previous instructions45. Intel® Advanced Vector Extensio...
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针对“普通级(以上)厨师”的高级计算机概念: 简介
作者:tianhui s. 张贴日期:2015/04/27 0
之前在与一位非常聪明但不是专业工程师的同事交谈时,我发现有必要对线程化和英特尔® 至强融核™ ⅹ100 和 ⅹ200 架构的其他组件稍作解释。 首先关于超线程,(说的更具体一点)以及协处理器的超线程版本。 经过冥思苦想,我终于想到可以用公共厨房来进行恰当的比喻。       了解处理器的超线程后,她提出了一些后续问题,以进一步讨论。 随着谈话的深入,我意识到,厨房这一比喻是一种比较恰当的表达方式,能够以直观且(相对)非技术化的方式解释处理器广义上的工作原理,以及 Knights 系列处理器所具备的最新创新功能。 Knights 系列包括之前...
视频 - 借助英特尔至强融核协处理器实现并行编程和优化
作者:tianhui s. 张贴日期:2015/04/27 0
下面是 Colfax International 发布的一组关于借助英特尔(R) 至强融核(TM) 协处理器实现并行编程和优化的视频。 第 2.1 集 MIC 架构的用途 在本段视频中,我们将介绍基于英特尔集成众核(或 MIC)架构的英特尔至强融核协处理器,以及硬件实施的几点特性。 第 2.2 集 英特尔 MIC 架构详情 本视频将详细介绍英特尔 MIC 架构的一般属性,然后重点介绍矢量指令支持。 第 2.3 集- 英特尔架构对矢量指令的支持 在本段视频中,我们将介绍矢量指令,以及英特尔至强融核协处理器支持的指令。 请点击此处的链接,观看更多 Colfax Internat...
视频 - 借助英特尔至强融核协处理器实现并行编程
作者:tianhui s. 张贴日期:2015/04/27 0
Colfax International 最近发布了下列一组关于英特尔(R) 至强融核(TM) 协处理器的视频。 面向英特尔至强协处理器的软件工具 该视频主要介绍了开发面向英特尔至强融核协处理器的应用时所需要并推荐采用的软件工具。 我们首先介绍启动协处理器以及运行预编译的可执行文件所需的软件。 我的应用是否能受益于 MIC 架构 在本视频中,我们将探讨可在英特尔至强融核协处理器上有效运行的应用类型。 我希望上述介绍能够帮助大家回答“我的应用是否能受益于 MIC 架构?” Knights Landing:未来的众核架构 本视频将介绍下一代 MIC 架构,该架构基于代号为 “Kn...
针对“普通级(以上)厨师”的高级计算机概念: 术语(第 1 部分)
作者:tianhui s. 张贴日期:2015/04/27 0
开始之前,我想通过下面两篇博客解释一些术语。 如果对这些概念已经有所了解,可以直接跳至下一部分。  我建议所有软件读者参阅其他关于介绍线程的博客。 这个领域存在许多混淆,即使我们软件专业人员也无法避免。 我们首先来了解一下什么是处理器、CPU、内核以及封装。 电视等大众媒体在使用这些术语时通常比较随便。 然后我们介绍线程,尤其是硬件和软件线程之间的区别。 人们通常容易混淆这些不同线程之间的区别,即使计算机编程人员也不例外。 内核? CPU? 封装? 芯片? HUH? 请大家注意下图 CPU 的左侧。 在奔腾® 处理器时代,人们通常将计算机中执行程序指令的组件(即计算机的大脑)称为“...
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Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
作者:kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Memory access pattern for threads
作者:Sangamesh B.1
      I've one basic question on threads memory access pattern. Suppose the computer/system/node has two sockets, each socket has its own block of memory(shared among two sockets), each socket has 4 cores. If there are two threads running(forked from a single process, may be pthreads/openmp threads), and thread 1 is on socket 1 and thread 2 on socket 2. If thread 1 tries to access data from socket 2's block of memory, then whether access time for this is same as accessing the data from its own block of memory or different? 
Set OpenMP attributes within code
作者:Allen Barnett2
Hi: I have discovered that setting KMP_BLOCKTIME=0 results in the best performance of my Fortran code. (Not by much, really, but it is measurable over our entire test suite.) Is it possible to set this attribute through an API call? I don't want to depend on the end user having to set environment variables. Also related, there are some loops for which the GCC GOMP library gives the best results when the scheduling is declared as "guided". When compiled with the Intel compiler, however, it appears best to not declare the schedule as guided. Is there an API function which can control the schedule for a given loop? Thanks, Allen  
Haswell Transactional Memory read/write-set information
作者:YangHun P.1
Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX). As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly) Then, Can I track transactional memory operations and get information like address, and values of read/write-set?
I have a problem with igzip
作者:gq L.2
Hi! I am studying about compression algorithm and software. I have question about igzip. I download igzip library in intel homepage. But I don`t know how to make wrapper. Can you send me 'example of wrapper' or 'example code' or 'manual'? I read homepage and saw a simple application. I don`t know how to input target file for compression and to output compression file and how to decompression? Do I make code about 'fast_lz and init_stream' function by myself? Plz help me. thank you
PCM reporting lower than expected memory read counts
作者:Patrick L.2
I have a piece of code on which I'm running PCM (Performance Counter Monitor). It is essentially the following: uint64_t *a,*b; a = new uint64_t[LEN]; b = new uint64_t[LEN]; for( int i=0;i<LEN;i++ ) a[i] = b[i];With LEN set to 402,653,184 (384 Mi), PCM is reporting 0.72 GB under READ and 6.30 GB under WRITE. Given that each array is 3 GiB, I would expect that both arrays would be read (since processor uses write-allocate), giving a READ of about 6 GiB. I would expect array "a" to be written back, giving a write count of 3 GiB. Does anyone know why the read count is so low, and the write count is higher than expected? Processor is Intel Core i7 940 (Nehalem). Any help is appreciated. Patrick
igzip 'make' problem
作者:gq L.2
Hi   I download igzip_042.zip and modify YASM path of Makefile   but it doesn`t make .exe file   I don`t know igzip execution sequence   If you have document about igzip, plz share it.   Thank you
igzip 'make' problem
作者:gq L.1
Hi I download igzip_042.zip and modify YASM path of Makefile but it don`t make .exe file I don`t know igzip execution sequence If you have document about igzip, plz share it. Thank you
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