Article

Optimizing Memory Bandwidth in Knights Landing on Stream Triad

This document demonstrates the best methods to obtain peak memory bandwidth performance on Intel® Xeon Phi™ Processor (codenamed Knights Landing). This is done using STREAM* benchmarks, the de facto industry-standard benchmark for the measurement of computer memory bandwidth.
作者: Karthik Raman (Intel) 最后更新时间: 2019/07/29 - 07:59
Article

Recipe: LAMMPS* for Intel® Xeon Phi™ Processors

Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS) is a classical molecular dynamics code that can be used to model atoms, or, more generically, as a parallel particle simulator at the atomic, meso, or continuum scale.This code recipe describes how to get, build, and use the LAMMPS* code for the Intel® Xeon Phi™ processor and presents some performance comparisons.
作者: WILLIAM B. (Intel) 最后更新时间: 2019/06/14 - 11:50
Article

Recipe: Building and Running Soft Sphere Simulation for Intel® Xeon® Processors and Intel® Xeon Phi™ Processors

This article provides a recipe for how to obtain, compile, and run the Soft Sphere Simulation sample code with the sample workload on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
作者: 管理 最后更新时间: 2019/06/14 - 11:50
Article

Recipe: Building and Running Parallel Ocean Program (POP) for Intel® Xeon Phi™ Processors

I. Overview
作者: 最后更新时间: 2019/06/14 - 11:50
Article

Recipe: Using Binomial Option Pricing Code as Representative Pricing Derivative Method

Introduction
作者: 最后更新时间: 2019/03/21 - 12:08
Article

Recipe: Monte Carlo European Option Pricing for Intel® Xeon Phi® Processor

This article covers the Monte Carlo Methods using a simple quasi random number generator.
作者: 管理 最后更新时间: 2019/06/14 - 11:50
Article

Recipe: Building and Running MASNUM WAVE for Intel® Xeon Phi™ Processors

This article provides a recipe for how to obtain, compile, and run an optimized version of MASNUM WAVE (0.2 degree high resolution) workload on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
作者: 最后更新时间: 2019/06/14 - 11:50
Article

Recipe: Pricing Options Using Barone-Adesi Whaley Approximation

In this paper, we look at one of the successful efforts, pioneered by Barone-Adesi and Whaley, and apply the high performance parallel computing entailed in the modern microprocessors to create a program that can exceed our expectation for high performance with a suitable numerical result.
作者: 管理 最后更新时间: 2019/03/21 - 12:00
Article

Recipe: Building and Running VLPL-S for Intel® Xeon Phi™ Processors

This article provides a recipe for how to obtain, compile, and run an optimized version of VLPL-S on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
作者: 最后更新时间: 2019/06/14 - 11:50
Article

Recipe: RELION for Intel® Xeon Phi™ 7250 processor

This article provides a recipe for how to obtain, compile, and run an optimized version of relion-1.4 on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
作者: Yu-Ping Z. (Intel) 最后更新时间: 2019/06/14 - 11:50