Yep. Here is another blog series from yours truly. Unfortunately, it will delay my long awaited – at least by me – discussion on measuring power.
Here is a rough outline for the blogs:
We had an ask from one of the various "Birds of a Feather" meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences.
Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.
Intel® Math Kernel Library includes powerful and versatile random number generators that have been optimized to take full advantage of Intel
Power management policy has evolved over the years.
Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.
By Taylor Kidd, Intel Corporation
This article is essentially a collection of blogs I wrote on the same subject. The differences are simply a degree of formalism.
While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the current and next generation Intel® Xeon Phi™ archit
Before we start, I will use the next two blogs to clear up some terminology. If you are familiar with these concepts, I give you permission to jump to the next section.