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Monitoring Intel® Transactional Synchronization Extensions with Intel® PCM

After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol

作者: Roman Dementiev (Intel) 最后更新时间: 2019/07/04 - 17:00
博客

Fun with Intel® Transactional Synchronization Extensions

By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).

作者: 最后更新时间: 2019/07/04 - 17:00
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

作者: Andreas Kleen (Intel) 最后更新时间: 2017/06/07 - 10:53
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

作者: 最后更新时间: 2019/07/06 - 10:52
Article

Intel® Xeon® Processor E7 v3 Product Family

作者: Nguyen, Khang T (Intel) 最后更新时间: 2019/07/06 - 16:40
博客

Debug Intel® Transactional Synchronization Extensions

If printf or fprintf functions cause transaction aborts, use Intel® Processor Trace as a work-around.
作者: Roman Dementiev (Intel) 最后更新时间: 2019/07/04 - 17:00
博客

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

作者: Roman Dementiev (Intel) 最后更新时间: 2019/10/08 - 18:20