博客

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

作者: Roman Dementiev (Intel) 最后更新时间: 2019/07/06 - 17:00
博客

Benign Data Races: What Could Possibly Go Wrong?

The peril of data races. Shows how even the most innocent ones can break badly.
作者: Dmitry Vyukov 最后更新时间: 2019/07/04 - 17:06
博客

Scope Oriented Programming

There is a long discussion talking about the advantages of Procedural Programming vs. the advantages of Object Oriented Programming.

作者: 最后更新时间: 2019/06/23 - 19:00
Article

Resource Guide for Intel® Xeon Phi™ Coprocessor Administrators

This article makes recommendations for how an administrator can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This article is 1 of 3: For the Administrator, for the Developer, and for the Investigator. Someone who will administer and support a set of machines (individual/cluster) containing coprocessors. The assumption is that the following topics are of...
作者: 最后更新时间: 2019/07/06 - 16:30
Article

Resource Guide for People Investigating the Intel® Xeon Phi™ Coprocessor

This article identifies resources for anyone investigating the value to their organization of the Intel® Xeon Phi™ coprocessor, which is based on the Intel® Many Integrated Core (Intel® MIC) archit

作者: 最后更新时间: 2019/06/14 - 12:10
博客

Debugging performance issues in Go programs

A comprehensive guide on performance debugging tools for the Go language.
作者: Dmitry Vyukov 最后更新时间: 2017/06/14 - 15:42
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

作者: 最后更新时间: 2019/07/06 - 10:52
Article

DrDebug : Linux* Command Line Usage

Using DrDebug requires following two phases 1. recording and 2. replaying.

作者: Harish Patil (Intel) 最后更新时间: 2019/02/12 - 10:56
Article

PinPlay* Testimonials

I. From Rice University
作者: Harish Patil (Intel) 最后更新时间: 2019/02/12 - 10:58
Article

PinPlay* FAQ

I. How long does record/replay take?

Record/replay overhead is a function of number of memory accesses and the amount of sharing in the test program.

作者: 管理 最后更新时间: 2019/02/20 - 12:40