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Intel® IPP Memory Function ippMalloc/Free FAQ

Information about Intel® Integrated Performance Primitives (Intel® IPP) memory functions
作者: 最后更新时间: 2019/07/31 - 14:30
Article

OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
作者: 最后更新时间: 2019/07/31 - 14:30
Article

Don't Spill That Register - Ensuring Optimal Performance From Intrinsics

This article helps developers ensure their C/C++ code with intrinsics produces the optimal assembly and shows how to spot unnecessary register spilling.
作者: 最后更新时间: 2017/06/07 - 09:24
Article

Threading Intel® Integrated Performance Primitives Image Resize with Intel® Threading Building Blocks

Threading Intel® IPP Image Resize with Intel® TBB.pdf (157.18 KB) :
作者: Jeffrey M. (Intel) 最后更新时间: 2019/07/31 - 15:05
Article

Fast Gathering-based SpMxV for Linear Feature Extraction

This algorithm can be used to improve sparse matrix-vector and matrix-matrix multiplication in any numerical computation. As we know, there are lots of applications involving semi-sparse matrix computation in High Performance Computing. Additionally, in popular perceptual computing low-level engines, especially speech and facial recognition, semi-sparse matrices are found to be very common....
作者: 最后更新时间: 2018/12/12 - 18:00
Article

Benefits of Intel® Optimized Caffe* in comparison with BVLC Caffe*

Overview
作者: JON J K. (Intel) 最后更新时间: 2018/05/30 - 07:00
博客

Question: Does Software Actually Use New Instruction Sets?

作者: Engblom, Jakob (Intel) 最后更新时间: 2019/07/04 - 16:56
Article

Intel® IPP - Threading / OpenMP* FAQ

This page contains common questions and answers on multi-threading in the Intel IPP.
作者: 最后更新时间: 2019/10/10 - 10:48
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
作者: 最后更新时间: 2019/10/15 - 15:30
博客

Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions

Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.

作者: gaston-hillar (Blackbelt) 最后更新时间: 2019/10/15 - 17:38