博客

Monitoring Intel® Transactional Synchronization Extensions with Intel® PCM

After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol

作者: Roman Dementiev (Intel) 最后更新时间: 2019/07/04 - 17:00
博客

TSX fallback paths

The need for fallback paths
作者: Andreas Kleen (Intel) 最后更新时间: 2017/06/14 - 13:26
博客

Fun with Intel® Transactional Synchronization Extensions

By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).

作者: 最后更新时间: 2019/07/04 - 17:00
Article

Using Intel® SDE's chip-check feature

Intel® SDE includes a software validation mechanism to restrict executed instructions to a part

作者: Mark Charney (Intel) 最后更新时间: 2019/05/31 - 09:04
博客

Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction

作者: 最后更新时间: 2018/05/28 - 18:30
博客

Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

In a previous post I discussed the Intel® Tra

作者: 最后更新时间: 2017/06/14 - 15:46
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

作者: Andreas Kleen (Intel) 最后更新时间: 2017/06/07 - 10:53
博客

Intel® Xeon® E5-2600 v3 Product Family

作者: Nguyen, Khang T (Intel) 最后更新时间: 2019/07/06 - 19:20
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

作者: 最后更新时间: 2019/07/06 - 10:52