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Multithreaded Code Optimization in PARSEC* 3.0: BlackScholes

Learn about the Blach-Scholes benchmark, part of the benchmark suite of multithreaded programs that comprise the Princeton Application Repository for Shared-Memory Computers (PARSEC).
作者: Artem G. (Intel) 最后更新时间: 2019/07/04 - 21:42
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Optimize Data Layout with SIMD Templates

Contrast results for manually tuning financial data and using data layout templates in the Intel® C++ Compiler.
作者: Nimisha R. (Intel) 最后更新时间: 2018/12/12 - 18:00
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Second Generation Intel® Xeon® Processor Scalable Family Technical Overview

New features and enhancements available in the second generation Intel® Xeon® processor Scalable family and how developers can take advantage of them
作者: David Mulnix (Intel) 最后更新时间: 2019/09/30 - 17:28
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Monte-Carlo simulation on Asian Options Pricing

This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
作者: Mike P. (Intel) 最后更新时间: 2019/09/30 - 17:28
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Case Study: Achieving High Performance on Monte Carlo European Option Using Stepwise Optimization Framework

Read this case study that discusses the Monte Carlo method of statistical computing to solve complex scientific computing problems.
作者: 最后更新时间: 2019/10/03 - 08:02
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Vector API Developer Program for Java* Software

This article introduces Vector API to Java* developers. It shows how to start using the API in Java programs, and provides examples of vector algorithms. It provides step-by-step details on how to build the Vector API and build Java applications using it. It provides the location for downloadable binaries for Project Panama binaries.
作者: Neil V. (Intel) 最后更新时间: 2019/10/15 - 15:30
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Case Study: Computing Black-Scholes with Intel® Advanced Vector Extensions

Case study discusses Intel® Advanced Vector Extensions (Intel® AVX), gives an overview of Black-Scholes valuation.
作者: 最后更新时间: 2019/10/15 - 15:30
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Intel Solutions and Technologies for the Evolving Data Center

  One Stop for Optimizing Your Data Center From AI to Big Data to HPC: End-to-end Solutions
作者: 管理 最后更新时间: 2019/10/15 - 17:00
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Optimizing the High Frequency Trading GatiRT* Application on the latest Intel® Architecture Server

By: Aditi Rathi (Intel) and Shailender Sharma (Gati)   ABSTRACT
作者: Aditi Rathi (Intel) 最后更新时间: 2019/10/15 - 19:56
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Accelerating Financial Applications on Intel® architecture

Learn more about an in-depth analysis of code modernization performance conducted by optimizing original CPU code and re-running tests on the latest GPU/CPU hardware.
作者: George Raskulinec (Intel) 最后更新时间: 2019/10/17 - 14:37