Dear passionate power management reader,
Yep. Here is another blog series from yours truly. Unfortunately, it will delay my long awaited – at least by me – discussion on measuring power.
Here is a rough outline for the blogs:
Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.
Power management policy has evolved over the years.
How about the future? Have we reached the pinnacle of power management?
While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the current and next generation Intel® Xeon Phi™ archit
Before we start, I will use the next two blogs to clear up some terminology. If you are familiar with these concepts, I give you permission to jump to the next section.
Last month there was a query on the IDZ MIC forum "how to perform inclusive scan in C cilk" in which my initial reply was:
Advanced Computer Concepts for the (Not So) Common Chef: Memory Hierarchy: Of Registers, Cache & Memory
After introducing this series of blogs, we established some