英特尔® 开发人员专区:
安全和加密

高级加密标准新指令

数字随机数生成器

英特尔指令集架构扩展

Intel® Trusted Execution Technology (Intel® TXT) Enabling Guide
By David Mulnix (Intel)Posted 03/28/20140
Download as PDF Contents   1 Overview of Benefits from Intel® Trusted Execution Technology (Intel® TXT) 2 Hardware and Software Prerequisites 2.1 Hardware-Layer Requirements 2.1.1 Processor 2.1.2 Chipset 2.1.3 BIOS 2.2 Software-Layer Requirements 2.2.1 Operating System and Hyp...
向安卓开发人员推介第四代英特尔® 凌动™ 处理器 BayTrail
By Mei-Lin H. (Intel)Posted 01/23/20140
下载 向安卓开发人员推介第四代英特尔® 凌动™ 处理器 BayTrail.pdf 摘要 英特尔已推出第四代英特尔凌动处理器,代号为 BayTrail。 这款最新凌动处理器是多核片上系统(SoC),集成了最新一代英特尔® 处理器内核、显卡、内存和 I/O 接口。 它还是英特尔基于 22 纳米处理器技术的首款片上系统。这一多核凌动处理器可提供出色的计算性能,能效也高于上代处理器。 除了采用最新 IA 内核技术,该处理器还提供众多平台特性,例如,显卡、连接、安全和传感器,支持开发人员开发用户体验极其丰富的软件。 本文主要介绍 BayTrail 对安卓的影响,英特尔为安卓架构提供的增强特性,...
Intel® Trusted Execution Technology
By Suman A Sehra (Intel)Posted 01/13/20146
Intel® Trusted Execution Technology (Intel® TXT) provides a hardware- based root of trust to ensure that a platform boots with a known good configuration of firmware, BIOS, virtual machine monitor, and operating system. For more information, please refer to http://www.intel.com/technology/malware...
Libcryptorandom
By John Mechalas (Intel)Posted 09/26/20130
Downloads Libcryptorandom [PDF 398KB]Libcryptorandom Source Code[ZIP 376KB] Libcryptorandom is a cross-platform library that allows programmers to obtain cryptographically secure random numbers from the best available entropy source on the underlying system. The library frees the programmer from ...

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英特尔® 虚拟化技术(英特尔® VT)

英特尔® 硬件加速执行管理器
By adminPosted 01/27/20140
最新更新:2013 年 11 月 5 日 英特尔® 硬件加速执行管理器是一个硬件辅助的虚拟化引擎(hypervisor,虚拟机监视器),它使用英特尔® 虚拟化技术加速安卓应用在主机上的模拟。英特尔® 硬件加速执行管理器与英特尔提供的安卓 x86 模拟器映像及官方Android SDK Manager(安卓软件开发套件)相结合,可在启用英特尔虚拟机的系统上更快地模拟安卓系统。 英特尔硬件加速执行管理器支持以下平台: Microsoft Windows* Windows 8(32/64 位)、Windows 7(32/64 位)、Windows Vista*(32/...
Intel® Hardware Accelerated Execution Manager
By HAOREN J. (Intel)Posted 11/27/20138
Last Updated April 15, 2014 The Intel Hardware Accelerated Execution Manager (Intel® HAXM) is a hardware-assisted virtualization engine (hypervisor) that uses Intel Virtualization Technology (Intel® VT) to speed up Android app emulation on a host machine. In combination with Android x86 emulator...
Intel® SDK for OpenCL* Applications - Performance Debugging Intro
By Maxim Shevtsov (Intel)Posted 11/08/20132
To the Intel® OpenCL SDK page Table of Contents 1. Host-Side Timing 2. Wrapping the Right Set of Operations 3. Profiling Operations Using OpenCL Profiling Events 4. Comparing OpenCL Kernel Performance with Performance of Native Code 5. Getting Credible Performance Numbers 6. Using Tools Download...
Intel oVirt Worksop
By Hai Shen (Intel)Posted 07/04/20130
回到英特尔学术社区首页>> Intel oVirt Worksop | May 2013 | Shanghai, China  Ovirt strives to become the first and best truly open and comprehensive data center virtualization management suite. As the oVirt community is rapidly evolving and growing, one of the ways we look to connect is through oVirt W...

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Intel感知计算(1)- 简介
By yanqing-wang (Intel)Posted 12/09/20121
Intel感知计算(1)- 简介 Intel感知计算通过设备感知和理解用户行为来进行人机交互,它是更加自然的、身临其境的、直觉交互方式。现在Intel感知计算SDK Beta版本已经能够使用,网友可以访问http://software.intel.com/en-us/vcsource/tools/perceptual-computing-sdk 来下载安装文件,如图1所示: 图1 先在图1右侧下来框中选择Perceptual Computing,然后在点击Download按钮。   Intel感知计算支持多种使用模式,比如说: l  语言认知              图2 l  ...
探讨i++和++i
By Jiaping Gui 桂佳平 (Intel)Posted 06/11/201281
最近笔者在调试代码时发现自己在对++运算符的理解上不够深入,导致一个不应有的bug的出现。 在代码书中或课堂上我们都知道++i和i++在作为一个单独语句使用时没有区别,即相当于i=i+1; 而作为语句的一部分时,如a=++i; 和a=i++; ++i先执行加1操作,再执行赋值操作(因++在前),而i++是先执行赋值操作,再执行加1操作(因++在后)。但这种论述未将其中更深的运行机制讲出来,尤其是在if或while等判断语句中,下面对其进行探讨: 作为单独语句存在,如下面的两段代码: int i=0; if(i++){...} int i=0; if(++i){.....
HTML5之Web Storage
By zheng-zhang (Intel)Posted 12/26/20112
WebStorage的出现是为了弥补cookie的不足,cookie一方面是容量小,4k/8k,存几个电子邮件都不够,二来是全局的,容易被误用,盗用。 在HTML5中网络存储按照生命周期分为2种,一种是基于会话(session),这种存储周期只是当前会话,当网页[注1]被关被后,或者被转到其他网站后,存储也就被销毁; [js] sessionStorage.varName = “生成新变量”; sessionStorage.varName = “变量操作”; delete sessionStorage.varName; //删除变量 [/js] 另外一种是本地存储,当网页下次被打开的时候...
当智能手机遇到了NFC
By yanqing-wang (Intel)Posted 11/01/20113
NFC(Near Field Communication)已经在国外搞得风生水起,在移动支付领域,以NFC手机为代表的新型支付已经向传统信用卡发起了挑战。特别是谷歌Android4.0(Icecream Sandwith)的一款叫Android Beam的应用,通过NFC通信,即时分享手机中的视频、文件和联系人信息等。它不仅推动了NFC在手机中的应用普,而且也使移动支付迈向一个新的阶段。        既然移动支付是未来的支付发展方向,那么为什么NFC的应用在国内却一直处于难产状态呢?笔者认为主要的原因如下:1)  标准问题。NFC进入中国,它首先遇到了两个行业老大:一是一掷千金的银联;...

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The action of Accessed and Dirty bit for EPT
By Arthur L.1
Hi there, I write a piece of code to test the action of Accessed and Dirty bit of EPT in Intel(R) Core(TM) i3-4130 CPU @ 3.40GHz. Firstly I build a totally new EPT paging structure with A/D logging on, then run some operating system codes and log all the EPT violation (say trap log). At some point I paused the OS, parse the EPT paging structure and log all the entries built in the past period (say A/D log). Here I get some interesting points: Some EPT entries are built without either Accessed or Dirty bit set, does this mean that CPU only construct these entries but doesn't touch them? Some entries only exist in A/D log. Does A/D logging module has some bias or some mistake? These two logs (trap log and A/D log) should be the same according to my understanding, and when I tried in the previous CPU with A/D bit supporting, these two logs are exactly the same, though I cannot distinguish Accessed or Dirty in A/D log.   Thanks ahead, Arthur
[x86] Information request about the Global Descriptor Table (GDT) | Intel® Developer Zone
By Jean M.2
Hello, I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things : GS is used as a segment selector (16 bits) : The lower three bits indicate the privilege level of access and the descriptor table to be used. In my case, we'll consider we use the GDT. The higher 13 bits represent the entry index in the GDT. Let's call A the base address corresponding to GTD[GS>>3]. A is returned, and the processor computes A+0x10 and gathers the value at this address, called B. A simple call B instruction is the executed. This kind of instruction happends when the code wants to perform a syscall : this instruction allows calling the __kernel_vsyscall function without knowing its address. Correct me if I'm wrong, but I understood that : The base address A corresponds to a section of the userland memory called the Thread Control Block (...
[x86] Information request about the Global Descriptor Table (GDT)
By Jean M.1
Hello, I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things : GS is used as a segment selector (16 bits) : The lower three bits indicate the privilege level of access and the descriptor table to be used. In my case, we'll consider we use the GDT. The higher 13 bits represent the entry index in the GDT. Let's call A the base address corresponding to GTD[GS>>3]. A is returned, and the processor computes A+0x10 and gathers the value at this address, called B. A simple call B instruction is the executed. This kind of instruction happends when the code wants to perform a syscall : this instruction allows calling the __kernel_vsyscall function without knowing its address. Correct me if I'm wrong, but I understood that : The base address A corresponds to a section of the userland memory called the Thread Control Block (...
Task Switch and Page Fault
By water m.2
Hi, What should I do when  handle task switch, but the new TSS is not in current virtual address space? Shoud I inject a Page Fault Exception to the guest directly?
handl I/O instruction caused VM-Exit
By water m.2
Hi, I'm writting code to handl I/O instruction caused VM-Exit, exit reason is 30.My guest is Windows XP. After get information from Exit Qualification, I can handle insturctions when String instruction bit and REP prefixed bit is cleared. But If these two bits are set, the trouble appears. When I tried to read data from memory where guest ESI(or EDI) pointed, I want to translate the logical address into physical address contained in guest  ESI(or EDI). but during the tranlsation,  the Page Table is not presented. At this time, I tried to inject a Page Fault to WindowsXP by set VM-entry interruption-information to 0x80000B0E,  VM-entry instruction length to 0x0, VM-entry exception error code to many kinds of possible number. But failed. I'am not sure whether my solution is correct. Can any one give me some tips?
Issue when the kernel parameter intel_iommu=on is being used
By sridhar s.1
Hello, I am using DPDK 1.5 for development of host pmd for device “Connect X3”. I am observing issue  while the ConnectX3 device DMA to a memory which is allocated with rte_memzone_reserve_aligned() API . The issue(please refer ERROR below) has been observed if the system runs with the kernel parameter “intel_iommu=on”. ########## ERROR :##################################3 dmar: DRHD: handling fault status reg 302 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f883000 DMAR:[fault reason 01] Present bit in root entry is clear #################################### The reported "fault Addr" is the physical address which was returned by the Above API. I don’t see any issue with the same code when the system up with kernel parameter intel_iommu=off.   If I use kernel parameters intel_iommu=on and iommu=pt, then the following error has been observed. ####ERROR REPORT######## dmar: DRHD: handling fault status reg 2 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f...
registering vm_exit handler in VT-x
By ivan i.1
Hi all, I would like to ask how an VM_EXIT handler is registered in VMCS - could you give some example. As far as i know VM_EXIT handler is routine, it could  be defined as C function. My question is how to register that handler function and to trap VM_EXITs into that function. Could you give some API  or snippet.  I have one more question ... when the VM_EXIT  handler is register and the execution meets the VM_EXIT conditions what is the mechanism of invoking the VM_EXIT handler? Is the invoking of the registered VM_EXIT handler is performed by VT-x at hardware level or there is something more to be done? Best Regards
EPT cause triple fault
By Mingbo Z.4
Hi all, I am writing a simple runtime hypervisor, like hyperdbg, bluepill. At first it works fine. But when I enable EPT, the vm exits with triple fault (Exit reason 2). and the guest RIP was at the fist instruction in non-root mode after vmlaunch. There is no ept violation. I did some 1:1 direct mapping, since no ept violation, that would be no use at all. wired thing is, the same code will run on VMware virtual machine. My PC is Core i7, and I disabled multicore. and I use serial port with windbg.  I am confused, which instruction caused this triple fault? I change the first line of non-root mode to "mov edi, edi", still the same triple fault.    Best regards, Mingbo

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