Intel Xeon Phi Coprocessor

Memory Management Optimizations on the Intel® Xeon Phi™ Coprocessor Using Abstract Vector Register Selection, _mm_malloc, mmap, and Prefetching

This article examines memory management performance optimization on the Intel® Xeon Phi™ using a non-library version of DGEMM. The performance optimizations incorporate dynamic storage allocation, high-level vector register management, and data prefetching. Code sample included.
  • 开发人员
  • Linux*
  • 服务器
  • C/C++
  • 高级
  • 英特尔® VTune™ 放大器
  • Intel Xeon Phi Coprocessor
  • Xeon Phi
  • DGEMM
  • prefetch tuning
  • 代码现代化
  • Intel® Many Integrated Core Architecture
  • A Brief Survey of NUMA (Non-Uniform Memory Architecture) Literature

    This document presents a list of articles on NUMA (Non-uniform Memory Architecture) that the author considers particularly useful. The document is divided into categories corresponding to the type of article being referenced. Often the referenced article could have been placed in more than one category. In this situation, the reference to the article is placed in what the author thinks is the most relevant category. These articles were obtained from the Internet and, though every attempt was made to identify useful and informative material, Intel does not provide any guarantees as to the veracity of the material. It is expected that the reader will use their own experience and knowledge to challenge and confirm the material in these references.
  • 开发人员
  • 教授
  • 学生
  • 服务器
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Landing
  • manycore
  • Many Core
  • KNL
  • 集群计算
  • 英特尔® 酷睿™ 处理器
  • Intel® Many Integrated Core Architecture
  • 优化
  • 并行计算
  • 平台分析
  • 线程
  • 矢量化
  • Coprocesador Intel® Xeon Phi™: catálogo de aplicaciones y soluciones

     

    El documento PDF que se adjunta a este artículo contiene una lista, en constante aumento, de código disponible, descargable o en elaboración que se puede ejecutar en coprocesadores Intel® Xeon Phi™ o que está siendo optimizado para ejecutarse en ellos.


  • Xeon Phi
  • Intel Xeon Phi Coprocessor
  • Knights Corner
  • Knights Landing
  • MIC
  • High performance computing
  • HPC
  • HPC applications
  • Parallel Programming
  • sample code
  • application modernization
  • application optimization
  • Intel® Many Integrated Core Architecture
  • Parallel Programming and Optimization with Intel® Xeon Phi™ Coprocessors Developer Training Event

    The 1-day seminar (CDT 101) features presentations on the available programming models and best optimization practices for the Intel Xeon Phi coprocessor, and on the usage of the Intel software development and diagnostic tools. CDT 101 is a prerequisite for hands-on labs, CDT 102.
    订阅 Intel Xeon Phi Coprocessor