For instructions such as VCVTSI2SD, your doc is clear. It says that in non-64 bit mode, W=1 will be have the same as W=0. That is, the second source will be 32 bits memory or a 32 bit GPR.
HOWEVER, AMD's doc says something different. I very rarely have seen any difference between Intel and AMD docs, and this is one such occasion. To me, it is very important for reasons of software compatibility to resolve any such differences.
In AMD Volume 4, page 101, it says: