Intel ISA Extensions

Behavior of some convert instructions with W=1 in non-64-bit mode

For instructions such as VCVTSI2SD, your doc is clear.  It says that in non-64 bit mode, W=1 will be have the same as W=0.  That is, the second source will be 32 bits memory or a 32 bit GPR.

HOWEVER, AMD's doc says something different.  I very rarely have seen any difference between Intel and AMD docs, and this is one such occasion.  To me, it is very important for reasons of software compatibility to resolve any such differences.

In AMD Volume 4, page 101, it says:

SGX support removed from Intel's ARK website?

Hi Intel


Until recently (1-2 weeks ago), Intel's ARK website listed SGX as being supported on the new Skylake 6600K and 6700K processors. However, this information now seems to have been removed? The page I'm talking about is (for the 6700K):

So does this mean SGX is no longer supported on these processors?



SGX extensions



With the new SGX extensions available in the new Skylake based CPU's (6700K and 6600K) I was wondering if Intel is ready to release more information about these technologies. Specifically:


1) Is there any plans for an emulator that can be used to emulate these technologies?

I210 driver delevopment (DOS)


I currently try to adapt firmware to new hardware. And have problems to get the I210 ethernet controler fetching DMA packets.

Old system: AMD Geode SC1200 Processor + Intel 82551
  - Firmware is a Win32 application using DOS + DOSExtender(DPMI)
  - The Intel 82551 Controller is directly controlled by firmware (NO DOS TCP/IP SOCKET)

Switching to protected mode clarification


I'm trying to understand a line in the Intel Architecture manual. It's a description of a possible failure situation when switching to protected mode.

Section 9.9.1 gives a recommended procedure for switching to protected mode. Step 3 is the mode switch, and step 4 is to immediately make a far transfer to initialize CS and cause serialization. The final paragraph says failures can occur if there are instructions between steps 3 and 4.

No explanation of comparison codes for integer vector compare instructions

In the ISE document 319433-022, instructions such as VPCMPD refer to an imm8 operand as a comparison predicate.  However, there is no explanation of the values of the predicate.

The Operation section of the instruction doc does indicate the 8 values of the low 3 bits.  But I only noticed this by chance.  It would be nice to have something in the Description section to refer the reader to the details.  Actually, why not use a similar language to that for VCMPPS, etc.

Wrong memory size for VGATHERQPS (?)

My version of the document, 319433-022, page 350 shows

EVEX.128.66.0F38.W0 93 /vsib
VGATHERQPS xmm1 {k1}, vm64x

I think this should be vm32x, not vm64x, since the operands are single-precision floats.

Similarly for the other two encodings of this instruction.

Please check other gather/scatter instructions that they are correct also.


What is syntax for broadcast decorator?

The ISE doc only describes the decorator syntax with the single example {1to16} (document 319433-022 page 7).

I would assume that generally you write {1ton} where n = the full vector size / the single element size.  But it would be nice to specify this exactly.

However, GNU `as` will not accept {1to4] or smaller.  Furthermore, it does not accept a broadcast decorator with a 128- or 256-bit vector size.  If I use .byte to assemble 128- and 256-bit instructions, the disassembler shows the {1to8} or {1to16} decorator regardless of VL.  Example:

IRET Pseudo-code Bug


I believe that there is a documentation bug in the pseudo-code for the IRET instruction in the current edition of Volume 2A of the Architectures Software Developers' Manual.

The case we're looking at is using IRET to switch from Ring-0 to Ring-3.

The prose for protected mode states:

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