英特尔® 开发人员专区:
虚拟化

英特尔® 虚拟化开发人员社区

开发人员,充分利用英特尔® 虚拟化技术。 参与我们的博客和论坛,并告诉我们什么对您很重要。 请告知我们您认为哪些方面很成功,同时我们可以对这一网站和其中的工具进行哪些改进,以便为您提供更大的帮助。

  • 入门
    • 针对虚拟化的智能排队技术 最近添加并仍然相关
    • 虚拟化入门
    • 虚拟化技术术语
    • 虚拟化使用模式
    • 在 VMware* 上创建虚拟机的教程
    • 为何软件厂商需要关注虚拟化
    • 英特尔® 定向 I/O 虚拟化技术(VT-d): 增强英特尔平台,实现 I/O 设备的有效虚拟化

    • 一些实用缩略语

      ATA 应用目标加速器
      BMC 底板管理控制器
      Boxboro 针对 Nehalem EX 的平台(英特尔® 至强™ 处理器 7500 系列和 Tukwilla)
      DCM 数据中心管理器
      EP 高能效表现
      EPT 扩展页表
      ESI 企业级南桥接口
      EX 可扩展服务器
      FBD 全缓冲 DIMM
      GT/秒 每秒十亿次传输
      HA 基于 QPI 的系统中的归属代理
      ICH IO 控制器中枢
      IMC 集成内存控制器
      IOH IO 中枢
      L1、L2 分别指一级和二级高速缓存
      LA 基板栅格阵列(一种芯片封装)
      LLC 最后一级高速缓存(每个芯片上)或最长延迟高速缓存
      MC 关键业务或多核
      MC 内存控制器
      ME 管理引擎
      NM 节点管理器
      NUMA 非一致性内存访问
      OEM 原始设备制造商
      PCI 外设组件接口(规范)
      QPI 快速通道互连(Pt 到 Pt 链路)
      RAS 可靠性、可用性、可维护性
      RMCP 远程监视和控制协议
      SCTP 流控制传输协议
      SDDC 单设备数据更正
      SKU 库存单位(即产品型号)
      SMB 可扩展内存缓冲
      SMB SMBus 系统管理总线
      SMI 可扩展内存接口
      SMT 线程 每个内核上的同步多线程线程数量或硬件 CPU 数量(如果启用为 2 个,如果不启用为 1 个)
      SSExy xy 代矢量指令 (9sTreaming SIMD 扩展)
      TDP 散热设计功率
      TPM 可信平台模块
      TPV 第三方厂商
      睿频加速 这一技术可支持一个或多个内核实现更高频率
      可信执行技术 可信执行技术
      Tylersburg 支持 Nehalem EP(英特尔® 至强™ 处理器 5500 系列)和 Westmere EP(英特尔® 至强™ 处理器 5600 系列)的平台
Intel® System Studio 2014 Beta - Articles Archive
By Noah Clemons (Intel)Posted 02/19/20140
Overview What's New Overview Detailed New Feature Overview Intel® System Studio 2014 for Linux* - System Requirements Intel® System Studio - Perfect Fit for Wind River* Linux* (PDF) Build and Design for Performance Using Intel® Compiler in Eclipse* for Wind River* Linux* Devel...
Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview
By Sreelekshmy Syamalakumari (Intel)Posted 10/04/20133
Download Article Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview [PDF 780KB] Contents Executive Summary Introduction Intel Xeon processor E5-2600 V2 product family enhancements Intel® Secure Key (DRNG) Intel® OS Guard (SMEP) Intel® Advanced Vector Extensions (Intel® AVX): Floa...
Intel® System Studio 2014 for Linux* BETA - Release Notes
By robert-mueller-albrecht (Intel)Posted 09/28/20130
This page provides the current Release Notes for the Intel® System Studio 2014 BETA product. To get product updates, log in to the Intel® Software Development Products Registration Center. For questions or technical support, visit Intel® Software Products Support. Intel® System Studio 2014 BET...
Intel® System Studio 2014 for Linux* - Solutions, Tips and Tricks
By robert-mueller-albrecht (Intel)Posted 09/28/20130
Overview What's New Overview Detailed New Feature Overview Intel® System Studio 2014 for Linux* - System Requirements Intel® System Studio - Perfect Fit for Wind River* Linux* (PDF) Build and Design for Performance Using Intel® Compiler in Eclipse* for Wind River* Linux* Devel...
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The action of Accessed and Dirty bit for EPT
By Arthur L.1
Hi there, I write a piece of code to test the action of Accessed and Dirty bit of EPT in Intel(R) Core(TM) i3-4130 CPU @ 3.40GHz. Firstly I build a totally new EPT paging structure with A/D logging on, then run some operating system codes and log all the EPT violation (say trap log). At some point I paused the OS, parse the EPT paging structure and log all the entries built in the past period (say A/D log). Here I get some interesting points: Some EPT entries are built without either Accessed or Dirty bit set, does this mean that CPU only construct these entries but doesn't touch them? Some entries only exist in A/D log. Does A/D logging module has some bias or some mistake? These two logs (trap log and A/D log) should be the same according to my understanding, and when I tried in the previous CPU with A/D bit supporting, these two logs are exactly the same, though I cannot distinguish Accessed or Dirty in A/D log.   Thanks ahead, Arthur
[x86] Information request about the Global Descriptor Table (GDT) | Intel® Developer Zone
By Jean M.2
Hello, I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things : GS is used as a segment selector (16 bits) : The lower three bits indicate the privilege level of access and the descriptor table to be used. In my case, we'll consider we use the GDT. The higher 13 bits represent the entry index in the GDT. Let's call A the base address corresponding to GTD[GS>>3]. A is returned, and the processor computes A+0x10 and gathers the value at this address, called B. A simple call B instruction is the executed. This kind of instruction happends when the code wants to perform a syscall : this instruction allows calling the __kernel_vsyscall function without knowing its address. Correct me if I'm wrong, but I understood that : The base address A corresponds to a section of the userland memory called the Thread Control Block (...
[x86] Information request about the Global Descriptor Table (GDT)
By Jean M.1
Hello, I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things : GS is used as a segment selector (16 bits) : The lower three bits indicate the privilege level of access and the descriptor table to be used. In my case, we'll consider we use the GDT. The higher 13 bits represent the entry index in the GDT. Let's call A the base address corresponding to GTD[GS>>3]. A is returned, and the processor computes A+0x10 and gathers the value at this address, called B. A simple call B instruction is the executed. This kind of instruction happends when the code wants to perform a syscall : this instruction allows calling the __kernel_vsyscall function without knowing its address. Correct me if I'm wrong, but I understood that : The base address A corresponds to a section of the userland memory called the Thread Control Block (...
Task Switch and Page Fault
By water m.2
Hi, What should I do when  handle task switch, but the new TSS is not in current virtual address space? Shoud I inject a Page Fault Exception to the guest directly?
handl I/O instruction caused VM-Exit
By water m.2
Hi, I'm writting code to handl I/O instruction caused VM-Exit, exit reason is 30.My guest is Windows XP. After get information from Exit Qualification, I can handle insturctions when String instruction bit and REP prefixed bit is cleared. But If these two bits are set, the trouble appears. When I tried to read data from memory where guest ESI(or EDI) pointed, I want to translate the logical address into physical address contained in guest  ESI(or EDI). but during the tranlsation,  the Page Table is not presented. At this time, I tried to inject a Page Fault to WindowsXP by set VM-entry interruption-information to 0x80000B0E,  VM-entry instruction length to 0x0, VM-entry exception error code to many kinds of possible number. But failed. I'am not sure whether my solution is correct. Can any one give me some tips?
Issue when the kernel parameter intel_iommu=on is being used
By sridhar s.1
Hello, I am using DPDK 1.5 for development of host pmd for device “Connect X3”. I am observing issue  while the ConnectX3 device DMA to a memory which is allocated with rte_memzone_reserve_aligned() API . The issue(please refer ERROR below) has been observed if the system runs with the kernel parameter “intel_iommu=on”. ########## ERROR :##################################3 dmar: DRHD: handling fault status reg 302 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f883000 DMAR:[fault reason 01] Present bit in root entry is clear #################################### The reported "fault Addr" is the physical address which was returned by the Above API. I don’t see any issue with the same code when the system up with kernel parameter intel_iommu=off.   If I use kernel parameters intel_iommu=on and iommu=pt, then the following error has been observed. ####ERROR REPORT######## dmar: DRHD: handling fault status reg 2 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f...
registering vm_exit handler in VT-x
By ivan i.1
Hi all, I would like to ask how an VM_EXIT handler is registered in VMCS - could you give some example. As far as i know VM_EXIT handler is routine, it could  be defined as C function. My question is how to register that handler function and to trap VM_EXITs into that function. Could you give some API  or snippet.  I have one more question ... when the VM_EXIT  handler is register and the execution meets the VM_EXIT conditions what is the mechanism of invoking the VM_EXIT handler? Is the invoking of the registered VM_EXIT handler is performed by VT-x at hardware level or there is something more to be done? Best Regards
EPT cause triple fault
By Mingbo Z.4
Hi all, I am writing a simple runtime hypervisor, like hyperdbg, bluepill. At first it works fine. But when I enable EPT, the vm exits with triple fault (Exit reason 2). and the guest RIP was at the fist instruction in non-root mode after vmlaunch. There is no ept violation. I did some 1:1 direct mapping, since no ept violation, that would be no use at all. wired thing is, the same code will run on VMware virtual machine. My PC is Core i7, and I disabled multicore. and I use serial port with windbg.  I am confused, which instruction caused this triple fault? I change the first line of non-root mode to "mov edi, edi", still the same triple fault.    Best regards, Mingbo

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David Ott: David 是英特尔软件解决方案事业部的高级软件工程师,最近的工作重心涉及企业级计算的各个方面,包括虚拟化、能效及安全性。 David 持有北卡罗来纳大学教堂山分校计算机科学专业的硕士和博士学位 。

Hussam Mousa 是英特尔系统优化技术中心 (SOTC) 的软件工程师。 他负责虚拟化性能分析,专注于企业级应用的 I/O 性能。 他在学术会议上发表过若干有关虚拟化性能分析的论文。 2002 年和 2010 年,他分别获得了开罗美国大学理学士学位和加州大学圣巴巴拉分校的博士学位,并于 2007 年加入英特尔至今。

Karthik Narayanan 是英特尔的软件工程师,负责以下方面工作:企业和管理应用、集群、高可用性、按需计算(本机和虚拟化)方面的工作。 他为英特尔工作了 4 年多,此前,他曾就职于纽约和印度的软件公司,获得了丰富的工作经验。 Karthik 获得了印度马德拉斯大学工程学士学位,及托莱多大学的计算机科学理学硕士学位。